package chipyard_learning.parameters

import chisel3._
import org.chipsalliance.cde.config._

case object WIDTH extends Field[Int]

class MyConfig extends Config((site, here, up) =>
  {
    case WIDTH => 8
  }) 

class HelloWorld (implicit p:Parameters) extends Module {
  val width: Int = p(WIDTH)
  val io = IO(new Bundle{
    val port_a = Input(UInt(width.W))
    val port_b = Input(UInt(width.W))
    val port_c = Output(UInt(width.W))
  })
  io.port_c := io.port_a + io.port_b
}

object HelloWorld extends App{
  implicit val parames: Config = (new MyConfig).toInstance
  (new chisel3.stage.ChiselStage).emitVerilog(new HelloWorld()(parames), Array("--target-dir", "verilog/output"))
}